An ongoing goal of the semiconductor industry is to reduce a size of individual memory cells of a memory array to occupy less area of a semiconductor substrate (often referred to in the industry as “real estate”) per memory cell. A memory cell, such as a dynamic random-access memory (DRAM) cell, typically includes a charge storage capacitor coupled to an access device, such as a field-effect transistor (FET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The access device applies or removes charge to the capacitor, such as during reading and writing operations. The charges stored on the capacitor are used to determine a logic state of the memory cell. In the ongoing goal to increase a packing density of memory cells of a memory array, a size of the capacitors may be reduced.
Capacitors may include a dielectric material disposed between two electrodes. A storage capacity of a capacitor is, at least in part, a function of properties (e.g., a dielectric constant) of the dielectric material. Capacitors including high-k dielectric materials exhibit a higher capacitance than those of similar size and configuration including a dielectric material having a lower dielectric constant. Conventional high-k dielectric materials include crystalline oxides exhibiting highly symmetric crystal structures (e.g., such as those that exhibit tetragonal or cubic crystal structures).
However, as feature sizes of memory cells are reduced, formation of dielectric materials capable of storing sufficient charges for operation of the memory cell becomes a challenge. For example, below a thickness of about 6 nm, formation of low-defect crystalline materials with a high dielectric permittivity is challenging. In addition, at such low thicknesses, many dielectric materials exhibit leakage currents and tunneling, reducing an amount of charge stored on the capacitor during use and operation. Further, at low thicknesses, the dielectric materials may exhibit polymorphism, leading to competing phases that are difficult to control. In some instance, the low thicknesses promote an amorphous phase. Some high-k dielectric materials include oxygen vacancies that serve as charge traps and increase leakage from the dielectric materials, as well as adversely affect endurance and device reliability.